Ring circuit



Dec. 8, 1964 L. R. ADAMS RING CIRCUIT Filed Jan. 30, 1961 2 Sheets-Sheetl B SHIFT /lWf/W/r LESTER R. ADAMS Dec. 8, 1964 Filed Jan. 30, 1961 L.R. ADAMS RING CIRCUIT 2 Sheets-Sheet 2 A SHIFT BSHIFT OUTPUT AT A2OUTPUT AT B2 OUTPUT AT A3 OUTPUT AT B3 )A OUTPUT AT TERMINAL B2A4 OUTPUTAT TERMINAL A4-B5 FIG. 2

3,l6d,862 RING CIRCUIT Lester R. Adams, Endwell, NSY., assigner tointernational Business Machines Corporation, New York, NSY., acorporation of New Yarn Filed Inu. 3l?, 1961, Ser. Ne. 85,805 S Claims.(Cl. 34th-U4) This invention relates to timing ring circuits and moreparticularly to a timing ring circuit comprising magnetic core elements.

Timing ring circuits have a variety of applications in computers andother related fields. In such circuits, it is desirable to form timingpulses adjacent to one another with las little delay as possible betweenpulses. Timing rings utilizing magnetic cores have a fewer number ofactive components than vacuum tube or transistor rings and thus are morereliable. Also, magnetic core rings offer space savings and, otherwise,are more economical than vacuum tube or transistor rings.

Accordingly, it is a principal object of the present in- Vention toprovide an improved ring circuit utilizing magnetic c'ores. l

In ring circuits, it isalso desirable to provide pulses which may be ofvarying lengths and may be generated at determined time intervals.

.Accordingly it is another object of the present invention to provide `atiming ring wherein the output pulse length and/or occurrence of thetiming pulses may be varied.

In the attainment of the foregoing objects, two similar andinterconnected registers are provided; each register comprises aplurality of cores connected in series. A storage means in the form of acapacitor is .utilized to temporarily store the output of each core;-the'output of each capacitor is connected as the input to the succeedingcore. The discharging of the capacitor in one register is controlled bythe shifting of the magneticstate of a core in the other register. As aconsequence, the discharging of a capacitor causes a succeeding core inthe same register to shift its magnetic state; shift pulses appliedduring the following timing period cause said succeeding core to shiftand cause its yassociated capacitor to charge. The cycle vis thenrepeated. The timing ring thus provides avseries of pulses which occurimmediately one after the other.

IThe foregoing and other objects, features and advantages of theinvention will be apparent from the follow- United States Patent ingmore particular description of a preferred einbodivment of theinvention, as illustrated in the accompanying succeeding core.

The magnetic cores utilized in the ring circuit of the invention havetwo stable states, that is, the cores have sufficient magneticretentivity to remain in the stable magnetic state to which they 'areshifted. For purposes of explanation, assume that 'a first, initial, orreset stable state is indicated by a 0 and a second or set stable stateis indicated by a 1. The various core stages are similar. As is known,the dots shown at each winding indicate the winding directions and theconvention is that a positive current into the dotted end of a windingsets i a core in state 1.

Each core in each of the registers includes an input winding a, a pairof output windings b and c, and a shift winding d. The output winding cof each of the cores is connected through a first diode f, and a seconddiode h to the input winding a of al succeeding core; lthe cathn ode ofdiode f is connected to the anode of diode h. One terminal of acapacitor g is connected to the junction of diodes f and h; the otherterminal of capacitor g is connected to a negative reference line 18;for simplicity in depicting the circuit in the drawing, two negativereference lines 18 are shown in FIG. 1. One terminal of each of theoutput windingsb of the cores in register I is connected to groundreference; the other terminal of each of windings b of the cores inregister I is connected in series with respective windings a of thecorresponding cores in'register II note, for example, winding b of core21 in register I connected in series to winding a in register II of core31. The other terminal of each of windings a of theV cores in registerII is connectedto the cathode of a preceding diode h. One terminal ofeach of windings bof the cores in register II is connected to groundreference; the other-terminal of each of windings b of the cores inregister IIis connected to one terminal of winding a of avrespectivelysucceeding core in register I; note, for example, Winding b of core 31in register II connected in series to winding a of core 22 in registerI.

Shift line 36 is connected in series to the shift wind ing d of each ofthe cores in register I. Likewise, shift line Y37' is connected inseries to the winding d of each of the cores in register II. Inopera-tion, it will be understood that shift pulses are alternativelyand continuously provided to shift lines 36 and 37 in FIG. 2, only thefirst shift pulse applied to each line is shown.

. The A1, B1, W, X and Y terminals shown at'the righthand or -top sideof the circuit, as oriented in FIG. 1,are

connected to the same numbered terminals on the lefthand or bottom sideof the circuit to form a ring. It will be appreciated that the totalnumber of stages employed in lthe timing ring is essentially unlimited,although only stages or cores 21-25 in register I and cores 31-35 inregister II`are shown.

Winding Inl coupled to core 21 of register I ma receivethe input signalto initiate thetiming operation. The output signals fromthe timing ringare takenfrorn the :terminals at the junction of capacitor g andfdiodesf and h which terminals are lettered :A1, A2 ASin Aregister' I, andwhich` terminals are lettered B1, B2

B5 in register II. l

As will beV explained in morefdetail hereinbelow, and

as shown in FIG. 1, circuit connectionscan be made to various otherpoints in the circuit to obtain different length pulses. For example, acircuit 19 including diodes and h', a capacitor g', and an outputterminal labeled B2-A4 is connected as follows: Diode f' has its anodeconnected to one terminal of output winding c of core 31 in register II;the cathode of diode f is connected to the anode of a second diode h andthe cathode of diode h' is connected to the junction of winding b ofcore 23 in register I and winding a of core 33 in register II. Acapacitor g has one terminal connected tothe junction of diodes f and h'and its other terminal connected to the negative reference potentialline 18. In FIG.;1, an-

other similar circuit 20 is .connected between Winding c 'of core 23 inregister I and winding b of core 34 in register II; other similarcircuits as desiredmay be connected to other points in the ring circuitto obtainV pulses which are initiated at different time intervals andhave a desired pulse length.

The operation of the circuit of FIG. 1 is as follows:

aisassz Y '3 Assume, initially all the cores in the ring are reset, thatis, at magnetic state 0. At time T1, see FIG. 2, winding Inl in registerI is energized and core 21 set to 1. At time T2, a negative A shiftpulse from suitable external circuitry, not shown, .is a-pplied to line36 to reset core 21 to 0. When core 21 is set to 0, Ja voltage is`induced across its ouput windings 'lv and. c; the voltage Ainduced inwinding c forward biases the associated :diode f and char-ges theassociated capacitor fg. rlhe volta-ge induced across winding 'b jcausescurrent ow v*through winding a Vof, core V3i in :register lI vand shiftscore 3l to state 1.

Nei/rt, at time T3, a negative ,B shift pulse, Valso from Asuitableexternal circuitry, not shown, is applied to line 37 to reset )core 3lto 0J Application of the B shift pulse produces three effects: first, itshifts core 31 vof register l1 to 0; then second, when core 31 .isshifted lor -reset to 0, a voltage .is induced in Vwindi-ng c of core 3i'to forward 'bias associated diode f and charge capacitor g associatedAwith core .31; and third, a voltage is induced in Winding 'b of coreY'31. 'Winding 5b -lof core 31 tends to generate a Ycurrent flow throughits series circuit including winding -a of-core '22 :and diodeSassociated with lcor'e 21. This causes fdiode h associatedrwith core 215to 'be 'forward lbiased and permits capacitor vg associated wit'h core221 vto fdischarge through Winding a fof core 22 in register I, andAthus vsets core 22 to 1. l

This completes the iirst cycle.

Note 'that at the terrn-ination'.of the first cycle, core 2?. inregister I is at state 0,core '31 in register IIfis at state 0, core'242Iin register I is at--state 1, and capacitor vfg associated withcore 'Sil is charged. v

Nexta negative shiftpulse is applied to fline 36. The

application 4of* 'the A vshift Jpulse does rthree things; rirst,

-it shifts core 22 of register ='I to f0; then second, Awhen 'core Y22is reset to 0, winding c of Icore 122 provides a voltage `to forwardbias its associateddiode f and charges its associated capacitor g; andthird, a voltage is induced inrwinding b of core 22. Winding b yof core2-2 tends lto generate a current dow through its `series circuit a'ofvcore 32, and diode h associated with core 31. vThiscauses-diode hassociated with core '22 to begfo'rward biased and permits capacitor- Agassociated 'With core l31 -to discharge through winding -a of core -32in register II, and thus sets core 32 lto 1. This completes the secondcycle.

Note that at theterm'ination of lthe second cycle, cores 21 and 22 inregister I are'at state 0j core 31- in register II is at state 0, core32 in register 4II is at state 1, and capacitor g associated with 'core22 is charged. v

The cycles of operation repeat down fthe line providing a series-ofoutput pulses at terminals, A2, B2, A3, B3, A4

The foregoing ring 'circuit provides pulses yof from 0.5 to 40microsecondsf duration and can thus bev used for Vapplications in thekilocycles. Y Y Y When itis desired -to generate a pulse of longerduration .as well las the'basic timing pulses, a diode-capacitor circuitsuch as f', g and h i'sfconnected at 'distinct pointson the ringcircuit. As noted hereinabove, the circuit including diode f', capacitorg anddiode h.' isl connected from one `terminal .of Winding `citothejunction of winding a associated with core 33 and winding bassociated with core '23. Thus, the voltage developedacross .winding c,when core to charge. Capacitor .g..maintains its lcharge untilzcore 23megacycle lrange downv to 20 or 30 Y I in time than the pulse obtainedat terminal B2-A4, as shown in FIG. 2.

It can be readily appreciated that the time at which a pulse output isinitiated can be determined by the point on the circuit at which theforemost connection of a circuit such as f', g and h is made. Also, theduration of the pulse can be determined bythe point on the circuit atwhich the other or after connection of the circuit f', g and h is made.

While the invention has been particularly shown and described withreference-to a preferred embodiment thereof, it will be understood bythose skilled in the art that various changes in form and details lmayvbe made 'therein Without departing from the spirit and scope of theinvention.

What is V'claimed is:

l. A circuit fory developing timing pulses comprising first and secondregisters, each register including a plurality Vof magnetic core stages-ar'rangedin a ring-circuit,each rof said cores having first andsecondstable conditions, the stages in Aone register being interconnected tocorresponding stages in the other register,-each core lhaving inputwindings lfor receiving -input pulses causing the core to change from aninitial condition to the -otherof its stable conditions., outputwindinvs on said cores, said out-putY windings producing anoutput pulse-When thecore changes from'itsinitial to its other stable condition, andshift ,windings for .receiving shift pulses to shift a core to itsinitial condition, means connected to an output Winding of each Vcorefor storing a pulse, gating means .for connecting ythe stored pulse fromsaid storing means Ato `,the windings of a selected succeeding 4core tothereby shift the stable condition of sa-id succeeding core, each gatingmeans also being connected to a winding of an associated core intheother register, leach gating meansyin a-register being activated tocou-ple the stored 1pulse -to a succeeding core when its associated corein ytheother register shifts stable conditions whereby output pulses areprovided which are initiated at a-determined time and areof a desiredlength.

2. A circuit 'for developing f timing pulses comprising a pair ofregisters, each register including a lplurality `of 'magnetic cores,each fof said cores having -irst and second magnetic stable conditions,first winding means Wound-onreach core `for shifting said cores to aVIirst stable condition, second winding means Wound on each core forshifting said cores fromaiirst to alsecond stable condition, outputwinding means wound on each core for providing voltage pulses when theassociated corey shifts stable conditions, a capacitor associated witheach core, alir'st unidirectional conducting device connecting an outputwind- ,iected core changes llfrorn r`its ifirst, Vto. its second stablecondition, a second unidirectional conducting device connected betweeneach capacitor and a selectedou'tput windingtmeans on a selected. eoreinthe .other register, the associated second conducting 'device Pbeingforward vbiased when' the selected'core in said other register .isVshifted to its second stable condition totherebyfcause the associatedcapacitor to discharge-through said selected core whereby inregister Iis caused-to shiftfrom state 1 to state "0 ilarly as above and providesan output a pulsejof relativel l-y `long time duration at terminalA4a-B5 at a -later point .and lthus to forward -bias diode `h',-asdiscussed hereinpulses of .variable .time duration may 'zbe provideddepend- .ent onthe connections ofasaidrst'and second conducting devicesto their associated 'cor-es.

3. .A circuit for developing timing pulses comprising iirst and secondregisters, each register including a pluralvity of magnetic coresarranged in a chain,;each of said cores having iii-.stand second stablemagneticconditions, a plurality of windings on eachcore, la irst Iofsaid windings onv each 'core being Aenergirable to shift the core Ato-its first stable condition, a second of said windings on each corebeingenergizable toshift the `core to .its second ystable condition, a thirdone of said windings on each core being connected 'from-one core in aregister tothe second winding on a corresponding core in 'the otherregister whereby the output pulse developed by said third winding whenthe associated core is shifted is connected to the second of saidwindings on the corresponding core in said other register to shift saidcorresponding core from its first to its second stable condition,capacitor means, a plurality of rst unidirectional conducting means eachconnecting a fourth winding of a core in one register to an associatedcapacitor means for storing the output pulse developed in said fourthwinding when the associated core is shifted from its second to its iirststable condition, and a plurality of second unidirectional conductingmeans each connecting an associated capacitor means to the third windingof a succeeding core in said other register, one of said secondunidirectional conducting means being forward biased when the associatedsucceeding core in said other register shifts from its second to itsfirst stable condition to thereby discharge said associated capacitorthrough said third winding of said succeeding core whereby pulses ofselected time duration may be provided by selectively connecting saidfirst and second unidirectional conducting means to the windings of saidcores in said registers. k

4. A circuit as in claim 3 in which said unidirectional conducting meansare diodes,

5. A system for providing timing pulses comprising first and secondregisters, each register including a plurality of saturable magneticcores cach having a first and second stable state, a core in oneregister having a corresponding core in the other register, each of saidcores having a plurality of windingswound thereon, a first of saidwindings on each core being energizableto Saturably magnetize theassociated core to its iirst stable state, a second of said windings oneach core being energizable to saturably magnetize the associated coreto its second stable state, a plurality of first gating means, eachgating means comprising a first and a second unidirectional conductingdevice connected in series, said first unidirectional conducting deviceof each gating means being connected to a third winding on an associatedcore, a capacitor means connected to each junction of saidfirst andsecond ing a voltage pulse, a second unidirectional conducting deviceconnecting the associated capacitor means to said second winding on thesucceeding core in a register for controllably gating a pulse from saidcapacitor means to said second winding of said succeeding core, a secondwinding of each core in one register being connected to said fourthwinding of a preceding core in the other register, a secondunidirectional conducting device being forward biased when the precedingcore in said other register is shifted to a first stable state whichenables the associated capacitor means to discharge through the secondwinding of the succeeding core in said one register whereby pulses areserially developed at the junction of said first and secondunidirectional conducting devices, a plurality of.second gating meanseach comprising first and second unidirectional conducting devicesconnected in series, second capacitor means connected to the junction ofsaid first and second unidirectional conducting devices of said secondgating means, said first unidirectional conducting device of a secondgating means being connected to the third winding of a selected core inone register, and said second unidirectional conducting device of saidsecond gating means being connected to the fourth winding of a selectedcore in the other register whereby pulses are provided at said junction`of said first and second unilateral conducting devices of said secondgating means, which pulses are initiated at a time and are of durationdependent on the selected cores to whose windings said first and secondunidirectional conducting devices are connected.

References Cited in the le of this patent UNITED STATES PATENTS2,654,080 Browne Sept. 29, 1953 2,730,695 Ziffer Jan. 10, 1956 2,832,951Browne Apr. 29, 1958 FOREIGN PATENTS 730,165 Great Britain May 18, 1955

5. A SYSTEM FOR PROVIDING TIMING PULSES COMPRISING FIRST AND SECONDREGISTERS, EACH REGISTER INCLUDING A PLURALITY OF SATURABLE MAGNETICCORES EACH HAVING A FIRST AND SECOND STABLE STATE, A CORE IN ONEREGISTER HAVING A CORRESPONDING CORE IN THE OTHER REGISTRY, EACH OF SAIDCORE HAVING A PLURALITY OF WINDINGS WOUND THEREON, A FIRST OF SAIDWINDINGS ON EACH CORE BEING ENERGIZABLE TO SATURABLY MAGNETIZE THEASSOCIATED CORE TO ITS FIRST STABLE STATE, A SECOND OF SAID WINDINGS ONEACH CORE BEING ENERGIZABLE TO SATURABLY MAGNETIZE THE ASSOCIATED CORETO ITS SECOND STABLE STATE, A PLURALITY OF FIRST GATING MEANS, EACHGATING MEANS COMPRISING A FIRST AND A SECOND UNIDIRECTIONAL CONDUCTINGDEVICE CONNECTED IN SERIES, SAID FIRST UNIDIRECTIONAL CONDUCTING DEVICEOF EACH GATING MEANS BEING CONNECTED TO A THIRD WINDING ON AN ASSOCIATEDCORE, A CAPACITOR MEANS CONNECTED TO EACH JUNCTION OF SAID FIRST ANDSECOND UNIDIRECTIONAL CONDUCTING DEVICES FOR RECEIVING AND STORING AVOLTAGE PULSE, A SECOND UNIDIRECTIONAL CONDUCTING DEVICE CONNECTING THEASSOCIATED CAPACITOR MEANS TO SAID SECOND WINDING ON THE SUCCEEDINGLYCORE IN A REGISTER FOR CONTROLLABLY GATING A PULSE FROM SAID CAPACITORMEANS TO SAID SECOND WINDING OF SAID SUCCEEDING CORE, A SECOND WINDINGOF EACH CORE IN ONE REGISTER BEING CONNECTED TO SAID FOURTH WINDING OF APRECEDING CORE IN THE OTHER REGISTER, A SECOND UNIDIRECTIONAL CONDUCTINGDEVICE BEING FORWARD BIASED WHEN THE PRECEDING CORE IN SAID OTHERREGISTER IS SHIFTED TO A FIRST STABLE STATE WHICH ENABLES THE ASSOCIATEDCAPACITOR MEANS TO DISCHARGE THROUGH THE SECOND WINDING OF THESUCCEEDING CORE IN SAID ONE REGISTER WHEREBY PULSES ARE SERIALLYDEVELOPED AT THE JUNCTION OF SAID FIRST AND SECOND UNIDIRECTIONALCONDUCTING DEVICES, A PLURALITY OF SECOND GATING MEANS EACH COMPRISINGFIRST AND SECOND UNIDIRECTIONAL CONDUCTING DEVICES CONNECTED IN SERIES,SECOND CAPACITOR MEANS CONNECTED TO THE JUNCTION OF SAID FIRST ANDSECOND UNIDIRECTIONAL CONDUCTING DEVICES OF SAID SECOND GATING MEANS,SAID FIRST UNIDIRECTIONAL CONDUCTING DEVICE OF A SECOND GATING MEANSBEING CONNECTED TO THE THIRD WINDING OF A SELECTED CORE IN ONE REGISTER,AND SAID SECOND UNIDIRECTIONAL CONDUCTING DEVICE OF SAID SECOND GATINGMEANS BEING CONNECTED TO THE FOURTH WINDING OF A SELECTED CORE IN THEOTHER REGISTER WHEREBY PULSES ARE PROVIDED AT SAID JUNCTION OF SAIDFIRST AND SECOND UNILATERAL CONDUCTING DEVICES OF SAID SECOND GATINGMEANS, WHICH PULSES ARE INITIATED AT A TIME AND ARE OF DURATIONDEPENDENT ON THE SELECTED CORES TO WHOSE WINDINGS SAID FIRST AND SECONDUNIDIRECTIONAL CONDUCTING DEVICES ARE CONNECTED.